1. Field of the Invention
This invention relates to a chip scale package (CSP), and more specifically to a method of making the chip scale package at the wafer level.
2. Description of the Related Art
As electronic devices have become more smaller and thinner, the velocity and the complexity of IC chip become more and more higher. Accordingly, a need has arisen for higher package efficiency. Demand for miniaturization is the primary catalyst driving the usage of advanced packages such as chip scale packages (CSP) and flip chips. Both of them greatly reduce the amount of board real estate required when compared to the alternative ball grid array (BGA) and thin small outline package (TSOP). Typically, a CSP is 20 percent larger than the chip itself. The most obvious advantage of CSP is the size of the package; that is, the package is slightly larger than the chip. Another advantage of CSP is that the package facilitates test and burn-in before assembly as an alternative to known good die (KGD) testing. In addition, CSP can combine many of the benefits of surface mount technology (SMT), such as standardization, encapsulation, surface mount, and reworkability, with the benefits of flip chip technology, such as low inductance, high I/O count, and direct thermal path.
However, CSP has at least one disadvantage compared to conventional BGA and TSOP, namely, high cost per unit. However, this problem could be eliminated if chip-sized packages could be mass produced more easily. Therefore, there is a need in the semiconductor packaging industry for CSP using mass production techniques at the wafer-level, as is illustrated in U.S. Pat. Nos. 5,977,624 and 6,004,867. Usually, methods of making wafer-level CSPs mainly comprise a step of attaching a substrate directly onto a wafer that is used prior to being diced into individual chips. The substrate includes a plurality of units corresponding to the chips on the wafer, and the dimensions thereof are substantially the same as the wafer.
Normally, the wafer is formed of microcrystalline silicon with a coefficient of thermal expansion (CTE) of 3-5 ppm/xc2x0 C. and the substrate is usually formed of polymer having a coefficient of thermal expansion of 20-30 ppm/xc2x0 C. Since there is a significant difference between the wafer and the substrate in CTE, the wafer and the substrate expand and contract in different amounts along with temperature fluctuations. This imposes both shear and bend stresses on the interface between the wafer and the substrate. Since the dimensions of the substrate are substantially the same as the wafer, the destructive stresses will accumulate. This greatly magnifies the reliability problems associated therewith.
Typically, the chips on the wafer go through a test to determine whether the chips are defective or not. After completing the testing process, at least some chips will be evaluated as defective. Therefore, in the conventional techniques described above, the substrate units attached on the defective chips are wasted. Similarly, it is very difficult to provide 100% good units on the substrate. Therefore, in the conventional techniques described above, the chips corresponding to defective units are also wasted.
Consequently, there is a need for a method of manufacturing chip scale packages at the wafer-level which reduces the problems and disadvantages associated with the above-described technique.
It is therefore an object of the present invention to overcome, or at least reduces the problems and disadvantages associated with the above-described technique for fabricating chip scale packages at the wafer-level
It is another objective of the present invention to provide a method for fabricating chip scale packages at the wafer-level in which the packaging yield is significantly enhanced.
The chip scale package in accordance with the present invention mainly comprises a substrate attached to the active surface of a semiconductor chip through an anisotropic conductive adhesive film (ACF). The substrate is provided with a plurality of contact pads on the lower surface thereof and a plurality of solder pads on the upper surface thereof wherein the contact pads are electrically coupled to corresponding solder pads. A plurality of metal bumps are provided on the contact pads of the substrate. The semiconductor chip has a plurality of bonding pads formed on the active surface thereof. The metal bumps on the substrate are electrically coupled to corresponding bonding pads on the chip through the ACF. The side portions of the substrate and the ACF are sealed in a package body.
According to the present invention, the method for manufacturing chip scale packages at the wafer-level comprises steps of: (a) providing a substrate strip including a plurality of substrates; (b) forming a plurality of metal bumps on the contact pads provided on the lower surface of each substrate; (c) attaching an anisotropic conductive adhesive film (ACF) onto the lower surface of the substrate strip to form a ACF/strip assembly; (d) cutting the ACF/strip assembly into individual substrates having ACF formed on the lower surface thereof; (e) attaching the substrates onto the chips of a wafer through the ACF formed on each substrate such that the metal bumps on each substrate are electrically coupled to corresponding bonding pads on each chip; (f) forming grooves corresponding to boundary regions between the chips; (g) sealing the grooves; and (h) cutting along the sealing grooves so as to obtain individual chip scale packages.
According to the present invention, the CSP manufacturing method is characterized in that each of the substrates is attached onto the chips of the wafer one by one. This greatly reduces the problems associated with CTE mismatch between the wafer and the substrate thereby significantly enhancing the product yield. Furthermore, we could attach only accepted substrates onto the wafer so as to avoid wasting good chips of the wafer.